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1 chip clp subsystem ic s1t8527c 1 introduction s1t8527c is a monolithic circuit which can be used in high performance 60mhz mca type clp system. the s1t8527c is a subsystem ic for fm / fsk receiving systems and a complete one chip fm / fsk receiver ic for 60mhz system. it ? s feature includes receiving functions for fm / fsk systems, a compander to remove external noise, and pll ( phase lock loop ) of channel selection which blocks surrounding frequency interference. the s1t8527c can be used with a wide range of fm / fsk vhf bandwidth systems, including cordless phone, and the narrow band voice and data sending / receiving systems. to make applications easily and simply, peripheral parts are minimized. features ? operating voltage range: 2.0v ? 5.5v ? typical supply current: 13.5ma at 3.6v ? built - in low battery detection function ( selectable 3.45v, 3.3v, 3.0v, 2.2v, 2.1v ) ? built - in speaker amplifier ? built - in splatter filter ? built - in dual conversion receiver, compander and universal pll ? fm receiver ? complete dual conversion circuit ? excellent input sensitivity (0.7 m vrms at 12db sinad) ? compader ? easy gain control to use external component ? included alc (automatic level control) circuit ? included mute logic ? universal pll ? rx (tx) divided counter range: 1/16 ? 1/16383 ? reference frequency divided counter range: 1/16 ? 1/4095 ? lock detector signal output ? serial interface with mcu for controlling each block ordering information device package operating temperature S1T8527C01-Q0R0 48 - qfp - 1010e - 20 c ? + 70 c 48 - qfp - 1010e
s1t8527c 1 chip clp subsystem ic 2 block diagram limiting if amp meter driver carrier detector rectifier gain cell regulator (1v) limiter gain cell rectifier if amp (455khz) 13 14 15 16 17 18 19 21 22 23 quad detector fsk comp alc 37 38 39 40 41 42 43 44 45 46 47 48 rx vco if amp (10.7mhz) 1st mix regulator ( 2.15 v ) programmable counter ( rx ) programmable counter ( tx ) programmable counter ( ref ) rx phase detector tx phase detector fmcu 4_25 cnt control buffer sum amp pri spk amp sum amp pri amp compandor mute spk amp x-tal osc low battery detector 2nd mix 35 34 33 32 31 30 29 28 27 26 25 12 11 10 9 8 7 5 4 3 1 2 - + vref + - crc co sfi sfo cdo/ldt gnd (pll) clk data lbd en agic pdt epi erc sai sao1 sao2 vcc (comp) gnd (comp) cpi+ cpi - alc 24 v ref (comp) 2mo vcc (rx) li ld gnd (rx) qci rao dsci dsco mdo 2loi 6 36 2loi gnd (pll) v ref (pll) 2mi 1loi 1loi 1mi tif 1mi 1mo v cc (pll) vco rx pdr 20 eo splatter filter
1 chip clp subsystem ic s1t8527c 3 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 epi erc eo sai sao1 sao2 vcc (comp) gnd (comp) cpi+ cpi - crc 2mo vcc (rx) li ld gnd (rx) qci rao dsci dsco mdo v ref(comp) alc kb8527b 14 15 16 17 18 19 20 21 22 23 24 13 47 46 45 44 43 42 41 40 39 38 37 48 36 35 34 33 32 31 30 29 28 27 26 25 co sfi sfo cdo/ldt gnd (pll) clk data lbd en agic gnd (pll) v ref(pll) 2loi 2loi 2mi 1loi 1loi 1mi tif 1mi 1mo v cc(pll) pdt vco rx pdr s1t8527c
s1t8527c 1 chip clp subsystem ic 4 pin description pin no symbol description 1 pdt3 phase detector output terminal of the transmitter at pll. if f tx > f ref or f tx is leading ? the output is negative pulse if f tx < f ref or f tx is lagging ? the output is positive pulse if f tx = f ref and the same phase ? the output is high impedance 2 co compressor output terminal of compander; connected to the splatter filter amp input terminal. 3 sfi input terminal of splatter filter amp. 4 sfo3 output terminal of splatter filter amp. 5 ldt/cdo ldt: output terminal of transmitter lock detector in pll block. the output is low if pll is in lock state and the output is high if pll is in unlock state. cdo: as an output terminal of the carrier detector buffer, connected to (rssi ) terminal of mcu. this pin outputs the contents of meter driver buffer which is turned on / off, according to the signal level detected by meter driver. 6 gnd pll ground. ground of logic section at pll. 7 8 9 clk data en these pins are serial interface terminals for programming reference counter, auxiliary reference counter, tx channel counter, rx channel counter and control block that controls internal each block with test mode and power saving mode. 10 lbd low battery detecting output. ( selectable 3.45v, 3.3v, 3.0v, 2.2v, 2.0v ). during the normal operation, output level is low, but it is high at low battery detection. as this pin is an open collector type, it requires a pull - up resistor. 11 agic this pin bypasses ac elements at the feedback loop which come from the sum amp block of compressor. a capacitor should be connected between this terminal and gnd. ( c = 2.2uf ) 12 crc converts waveform from the full wave rectifier to dc element at the rectifier block of compressor. ( rc = 33msec ) 13 cpi - pre-amp inverting input terminal of compressor. adjusts the negative feedback loop gain. ( in application, gain is 5 ) 14 cpi + pre-amp non-inverting input terminal of compressor. used as an input terminal for voice signals. 15 gnd (comp) ground of compander block. 16 vcc (comp) supply voltage. power supply terminal of compander. 17 sao 2 output terminal of speaker amp 2. this signal is the same as sao1 output, but phase difference is180 for sao1. dc voltage level is ( vcc ? 0.7v ) / 2.
1 chip clp subsystem ic s1t8527c 5 18 sao 1 output terminal of speaker amp 1. dc voltage level is ( vcc ? 0.7v ) / 2. 19 sai speaker amp 1 input terminal. between this terminal and expander output terminal, uses a ac coupled. 20 eo output terminal of expander, from which a regenerated voice signals are emitted. 21 erc converts waveform from the full wave rectifier to dc element at the rectifier block of expander. ( rc = 33 msec ) 22 epi - pre-amp inverting input terminal of expander. adjusts the negative feedback loop gain. ( in application, gain is 5 ). 23 alc reference current input terminal of automatic level control ( alc); adjusts thd of compressor output voltage to less than 3% or limits the frequency deviation of tx if the input is higher than a certain level. the alc circuit may be turned off depending on the alc reference current or the magnitude of output voltage may be limited if it is higher than a certain level. 24 v ref(comp) reference voltage ( v ref = 1v ). supplies a regulator voltage to the compressor and expander of compander. 25 mdo output terminal of the meter driver. amplitude of rf input signal for useful frequency is detected by meter driver circuit. the meter driver circuit has perfect linear characteristic of 60db range for input signal level. ( 0.1 m a / db ). 26 dsco output terminal of data slicing comparator. separates frequency shift keying ( fsk ) serial data and executes data shaping and limiting. 27 dsci input terminal of data slicing comparator. non-inverting type with the negative input terminal biased to 1/2 vcc. 28 rao recovered audio output terminal. voice signals detected by the quadrature detector are amplified and then output through this terminal. 29 qci3 quadrature coil input terminal. the 455khz oscillator circuit is an lp = 680uh, cp = 180pf valued lc tank circuit. voice signals are detected by mixture of 455khz ( by phase difference ) which is converted from mixer 2. 30 gnd rx ground . ground for receiver. 31 32 ld li limiter input and decoupling terminal. removes amplitude modulation elements caused by fading or fm signal noise. limiting if amplifies and limits the second intermediate frequency, 455khz.the input impedance of the limiting if amplifier is set to 1.5k w . while fm waves are transmitted with constant magnitude, their magnitudes are slightly modulated due to reflection from obstacles, fading phenomenon, noise wave, and mixing with am wave elements before entering the receiver ? s antenna.the limiter makes amplitude uniform by removing these am wave elements. pin description (continued) pin no symbol description
s1t8527c 1 chip clp subsystem ic 6 33 v cc(rx) supply voltage. supplies power to the receiver. 34 2mo3 output terminal of mixer 2. second intermediate frequency ( 455khz ), generated by mixing first intermediate frequency ( 10.7mhz ) and second local oscillator is output. 35 36 2loi 2loi input terminal of second local oscillator. generates second local oscillator frequency to convert output from mixer 1 ( 10.7mhz ) into second intermediate frequency. it is an oscillator with crystal of 10.24mhz and 10.245mhz. 37 2mi input terminal of mixer 2. output from mixer 1 is entered to mixer 2 input terminal via 10.7mhz ceramic filter. second mixer converts frequency to second intermediate frequency ( 455khz: am if ). 38 1mo3 output terminal of mixer 1. the signal from mixer 1 and the frequency of the first local oscillator are mixed to produce the first intermediate frequency, which is the output through this terminal. the output terminal is an emitter follower with an output impedance of 330 w to match the 330 w input/output impedance of the 10.7mhz ceramic filter. 39 40 1loi 1loi input terminal of the first local oscillator. the local oscillator is a voltage controlled oscillator. local oscillation frequency and received frequency are mixed at mixer 1 and then converted to the first intermediate frequency of 10.7mhz or 10.695mhz. 41 vco rx the terminal which variable capacitor is included in the chip. used as an input terminal where 1st local oscillation frequency is changed by varying the capacitor connected between 1st local oscillator terminals.the internal variable capacitor has the value of 18.73 ~ 15.86pf depending on the applied voltage. ( 1.0 ~ 2.0 v ). 42 43 1mi 1mi input terminal of mixer 1. this mixer is made of double balanced multiplier. the received signal amplified at rf amp is input to this terminal. 44 gnd (pll) ground. ground for analog at pll 45 pdr phase detector output terminal of the receiver at pll. if f rx > f ref or f rx is leading ? the output is negative pulse if f rx < f ref or f rx is lagging ? the output is positive pulse if f rx = f ref and the same phase ? the output is high impedance 46 v ref(pll) pll voltage reference output pin. an internal voltage regulator provides a stable power supply voltage for the rx and tx plls. 47 v cc(pll) power supply terminal of pll. 48 tif input terminal of tx channel counter. ac coupling with tx vco. minimum input level is 300mvp-p ( at 60mhz ). pin description (continued) pin no symbol description
1 chip clp subsystem ic s1t8527c 7 absolute maximum ratings current consumption at each mode ( vcc = 3.6v ) current consumption in each block ( vcc = 3.6v ) characteristic symbol value unit maximum supply voltage v cc 5.5 v power dissipation p d 600 mw operating temperature t opr - 20 ? + 70 c storage temperature t stg - 55 ? + 150 c modes min. typ. max. inactive mode - 350ua 600ua rx mode - 6.6ma - communication mode ( active mode ) - 13.5ma modes min. typ. max. receiver part - 5.0ma 7.5ma expander part - 1.4ma 2.1ma speaker part - 1.7ma 2.5ma compressor part - 3.0ma 4.5ma pll rx part - 1.6ma 2.4ma tx part - 0.8ma 1.2ma
s1t8527c 1 chip clp subsystem ic 8 electrical characteristics characteristic symbol test conditions min. typ. max. unit operating voltage vcc - 2.0 - 5.5 v receiver ( v cc = 3.6v, f c = 49.7mhz, f dev = 3khz, f mod = 1khz,ta = 25 c, unless otherwise specified ) input for - 3db sensitivity v lim - 3db point - 0.7 2.0 m vrms input for 20db sensitivity v i(sen) modulation input - 0.7 2.0 m vrms s/n ratio s/n modulation input no modulation input 48 55 - db recovered audio output v o(ra) rfin = 1mvrms 145 185 225 mvrms noise output level v no rfin = no input - 130 205 mvrms recovered audio output voltage drop v o(rad) vcc = 5v ? 2v rfin = 1mvrms - 8 - 3.3 - db detect output voltage v o(det) rfin = 1mvrms 1.0 1.5 2.0 v carrier detector threshold v th(det) rfin = no input 0.49 0.60 0.73 v comparator threshold voltage difference d v th v comp = 150mvp-p r l = 180k w 70 110 150 mv comparator output voltage 1 v oh v comp = 150mvp-p rl = 180k w 2.7 3.0 - v comparator output voltage 2 v ol v comp = 150mvp-p r l = 180k w - 0.25 0.5 v first mixer conversion voltage gain d g v(1m) v i(43) = 1mvrms r l(38) = 330 w 14 18 22 db second mixer conversion voltage gain d g v(2m) v i(37) = 1mvrms r l(34) = 1.5k w 17 21 25 db detector output distortion thd det rfin = 1mvrms - 1.5 2.5 % detector output resistance r o(det) rfin = 1mvrms - 1.2 - k w detector output dc voltage change ratio d v o(det) rfin = 1mvrms - 0.15 0.23 v/khz meter drive slope mds 70 100 135 na/db first mixer input resistance r i(1m) fc = 50mhz 500 690 - w first mixer input capacitance c i(1m) fc = 50mhz - 7.2 10 pf limiter input sensitivity v i(lim) fc = 455khz, 20db sinad - 100 250 m vrms second mixer input sensitivity s v(2m) fc = 10.7mhz, 20db sinad - 10 25 m vrms
1 chip clp subsystem ic s1t8527c 9 first mixer 3rd order sensitivity 3rd - - -22 - dbm low battery detector lbd3 lbd0?lbd3 = 0 ( default ) only lbd2 = 0 only lbd1 = 0 - 0.15 3.45 3.3 3.0 0.1 v only lbd3 = 0 lbd0 ? lbd3 = 1 - 0.1 2.2 2.1 0.075 am rejection ratio amrr rfin = 1mvrms ? 10mvrms am mod = 30% 25 25 - db compressor ( vcc = 3.6v, fc = 1khz, ta = 25 c, unless otherwise specified ) reference voltage v ref no signal 0.9 1.0 1.1 v standard output voltage vo(com) vinc = 13mvrms ( 0db ), ralc = gnd 255 300 345 mvrms compressor gain difference d gv1 (com) vinc=1.3mvrms ( - 20db), d gv1 (com) = 20 log (voc1/voc) + 10k - 1.0 - 0.5 - db d gv2 (com) vinc = 0.13mvrms ( - 40db) d gv2 (com) = 20 log (voc2/voc) + 20k - 2.0 - 1.0 - db compressor output distortion thd com vinc = 0db - 0.5 1.0 % mute attenuation ratio att mute vinc = 0db 60 80 - db compressor limiting voltaget v lim(com) vinc = variable 1.41 1.65 1.83 vp-p alc v alc i alc = 8ua ( r alc = 120k w ) 280 330 380 mvrms splatter filter vo(sf) vinc = 13mvrms = 0db 255 300 345 mvrms expander (vcc = 3.6v, fc = 1khz, ta = 25 c, unless otherwise specified) standard output voltage v o(exp) vine=30mvrms ( 0db ) 104 130 156 mvrms electrical characteristics (continued) characteristic symbol test conditions min. typ. max. unit
s1t8527c 1 chip clp subsystem ic 10 expander gain difference d g v1(exp) vine = 9.5mvrms ( - 10db) d gv1(exp) = 20 log (voe1/ voe) + 20 0 0.5 1.0 db d g v2(exp) vine = 3mvrms ( - 20db) d gv2 (exp) = 20 log (voe2/voe) + 40t 0 1.0 2.0 db d g v3(exp) vine = 0.95mvrms ( - 30db) d gv3 (exp) = 20 log (voe3/voe) + 60k 0 1.5 3.0 db expander output distortion thdexp vine = 0db - 0.5 1.0 % mute attenuation ratio attmute vine = 0db 60 80 - db expander maximum output voltage v oexp(max) vine = variable thd = 10%l 500 600 - mvrms speaker amp output 1 vo( sa1) vine = 30mvrms = 0 db 104 130 156 mvrms speaker amp output 2 vo( sa1) vine = 30mvrms = 0 db 104 130 156 mvrms pll ( vcc = 3.6v, ta = 25 c, unless otherwise specified ) operating current i ccpll vcc = 3.6v - 2.0 3.5 ma input current i ih vin = vcc - - 5 m a i il vin = 0v - 5 - - m a input voltage v ih - vcc-0.3 - - v v il - - - 0.3 v output current i oh vout = vcc 0.3 - - ma i ol vout = 0v 0.3 - - ma output voltage v oh1 pdt, pdr: io = - 0.3ma ( sourcing ) vcc-0.4 - - v v ol1 pdt, pdr: io = 0.3ma ( sinking ) - - 0.4 v v oh2 ld, fmcu: io = - 0.1ma ( sourcing ) vcc-0.5 - - v v ol2 ld, fmcu: io = 0.1ma ( sinking ) - - 0.5 v pll regulator voltage v pllreg 1.95 2.15 2.25 v electrical characteristics (continued) characteristic symbol test conditions min. typ. max. unit
1 chip clp subsystem ic s1t8527c 11 pll program summary mcu ( micom ) serial interface ( msb : 1st input ) use clk (pin 7 ), data (pin 8 ) , en (pin 9 ) terminals for program. data and clk terminals are used for loading data to internal shift - register. when en terminal is ? low ? it is possible to program tx-channel counter, rx - channel counter and various control functions of pll. when en terminal is ? high ? program 1st local oscillator capacitor selection in receiver for u.s.a - 25 ch function. ? tx - register, rx-register, control register ? reference - register ? receiver -1st local oscillator internal capacitor selection register & low battery detector voltage register [ clo_lbd-register ] pmc0 pmc1 14 bit data msb lsb data en clk en pmc0 pmc1 uk_s1 uk_s0 12 bit data data msb lsb clk data en clk msb lsb <1> pmc lbd3 lbd2 lbd1 lbd0 clo5 clo4 clo3 clo2 clo1 clo0
s1t8527c 1 chip clp subsystem ic 12 ? programmable counter ? rx - counter: setting frequency for rx.vco ( 14 bits --> 1/16 ? 1/16383 ) [ default_ch. = usa_#21 ( remote ): 36.075mhz ( div._no = 7215 )]c < rx. register (16bits) > ? tx - counter: setting frequency for tx.vco ( 14 bits --> 1/16 ? 1/16383 ) [ default_ch. = usa_#21 ( remote ): 49.830mhz ( div._no = 9966 )]' < tx. register (16 bits) > * program mode control bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 name pmc0 pmc1 d13 d12 d11 d10 d9 d8 default value 7215 * 0 1 1 1 0 0 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name d7 d6 d5 d4 d3 d2 d1 d0 default value 7215 0 0 1 0 1 1 1 1 bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 name pmc0 pmc1 d13 d12 d11 d10 d9 d8 default value 9966 * 0 1 1 1 0 0 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name d7 d6 d5 d4 d3 d2 d1 d0 default value 9966 1 1 1 0 1 1 1 0 pmc0 pmc1 program mode pmc0 pmc1 program mode 0 0 control block 0 1 upll_rx. block 1 0 upll_ref. block 1 1 upll_tx. block
1 chip clp subsystem ic s1t8527c 13 ? ref - counter: setting reference frequency for phase detector ( 12 bits --> 1/16 ~ 1/4095 ) [ default_divider = 2048, x-tal_osc = 10.240 mhz --> fref = 5khz ] < ref. register (16bits) > ? uk_selection figure 1. < reference frequency selection > bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 name pmc0 pmc1 uk_s1 uk_s0 d11 d10 d9 d8 default value 2048 * ref.freq. selection for united kingdomd 1 0 0 0 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name d7 d6 d5 d4 d3 d2 d1 d0 default value 2048 0 0 0 0 0 0 0 0 uk_s0 uk_s1 fr1 fr2 freftx frefrx 0 0 fref (a) - fref (a) fref (a) 1 0 fref (a) fref/4 (b) fref/4 (b) fref/4 (b) 0 1 fref/4 (b) fref/25 (c) fref/4 (b) fref/25 (c) 1 1 fref/4 (b) fref/25 (c) fref/25 (c) fref/4 (b) 12 bits reference program divider. pd_tx pd_rx ld pdt pdr fref (a) (b) (c) fr1 fr2 ? 4 ? 25 fref ? 4 fref ? 25
s1t8527c 1 chip clp subsystem ic 14 ? control program ? control register (16 bits) *** test mode & ldt-cdo mode bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 name pmc0 pmc0 - pll tx -bs co_m co_bs co_bs ex_bs description program mode control_0 program mode control_1 don ? t care pll_tx battery save compress or mute selection compress or battery save expander mute selection expander battery save function * program latch assign don ? t care 0:normal (pll_tx-on) 1:pll_tx power-off 0:normal 1:mute 0: co-on 1: normal ( co-part power-off ) 0:normal 1:mute 0: ex-on 1: normal ( ex-part power-off ) bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name ldt_ cdo lbd-bs rx-bs - - - test2 test1 description ldt or cdo select low battery detector battery save rx battery save don ? t care don ? t care don ? t care test mode 2 test mode 1 function ldt or cdo select 0:normal (lbd-on) 1:lbd-part power-off 0:normal (rx-on) 1:rx-part power-offf - * * * function test on each block of upll ldt/cdo test1 test2 ldt / cdo remark 0 0 0 rx block cdo default 1 0 rx block cdo 0 1 4_25cnt block fr2 1 1 4_25cnt block fr2 1 0 0 pll block ldt 1 0 pll block ldt 0 1 pll block ldt 1 1 test pll_tx
1 chip clp subsystem ic s1t8527c 15 ? operating internal circuit blocks in each mode ? clo_lbd - register program [ rx - 1 ? st local oscillation internal cap. for u.s.a - 25ch & alarm sensor detect voltage ] ? clo register ( 6 bits ) : receiver 1 ? st local oscillator internal capacitor selection *****pmc ( program mode control ) pmc = ? high ? & en = ? high ? ---> clo_lbd register program modeap ? rx - low battery detect voltage mode ( state ) operating circuit blocks active state ( communication mode ) pll regulator/micom i/f ( data, clk, en ) / 2nd local oscillator / receiver / 1st local oscillator / rx pll / carrier detector / fsk comparator / low battery detector / tx pll / expander & speaker amp / compressor / splatter filter amp receiving mode pll regulator / micom i/f ( data, clk, en )/ 2nd local oscillator / receiver / 1st local oscillator / rx pll / carrier detector / fsk comparator / low battery detector. inactive state pll regulator / micom i/f( data, clk, en ) bit bit10 (msb) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name pmc clo5 clo4 clo3 clo2 clo1 clo0 default value 0 1 * * * * * 0 0 0 0 0 0 function - 0:normal 1:internal cap. for usa 25 channel = 4.4pf 0:normal 1:internal cap. for usa 25 channel = 1.0pf 0:normal 1:internal cap. for usa 25 channel = 3.6pf 0:normal 1:internal cap. for usa 25 channel = 2.4pf 0:normal 1:internal cap. for usa 25 channel = 1.2pf 0:normal 1:internal cap. for usa 25 channel = 0.6pf bit bit 10(msb) bit 9 bit 8 bit 7 bit 6 low battery detector voltagef remark name pmc lbd3 lbd2 lbd1 lbd0 default value 1* * * * * 0 0 0 0 - default function 1 0 0 0 0 3.45v - 1 0 1 1 3.3v - 1 1 0 1 3.0v - 0 1 1 1 2.2v - 1 1 1 1 2.1v -
s1t8527c 1 chip clp subsystem ic 16 ***** pmc ( program mode control ) pmc = ? high ? & en = ? high ? ---> clo - lbd register program mode example 1 > low battery detector voltage : 2.1v u.s.a _ch-#1 ( remote ) ---> 1st local osc. varicap value = 15.86pf, internal cap = 7.0pf ( ext_l = 0.45uh, ext_c = 30pf ) ? 12 bit data format in case the 12 bits programming, insert 1 don ? t care bit ( dummy bit ) between pmc and lbd3. ? in case of setting 16 bit data format in case of 16 bits programming, insert 5 don ? t care bits between the pmc and lbd3 data en clk msb lsb pmc lbd3 lbd2 lbd1 lbd0 clo5 clo4 clo3 clo2 clo1 clo0 1 1 1 1 1 0 1 1 1 0 0 1( 0 ) dummy bit data en clk msb lsb pmc lbd3 lbd2 lbd1 lbd0 clo5 clo4 clo3 clo2 clo1 clo0 1 1 1 1 1 0 1 1 1 0 0 1( 0 ) dummy bit 1( 0 ) 1( 0 ) 1( 0 ) 1( 0 )
1 chip clp subsystem ic s1t8527c 17 example data for u.s.a 25_channel selection ? phase detector / lock detector output waveforms 1?st local osc. internal capacitor select base channels hand channels varicap value external c external l internal c bit5 (clo5) bit4 (clo4 bit3 (clo3) bit2 (clo2) bit1 (clo1) bit0 (clo0) 1 ? 25ch. 1 ? 25ch. 1.0v?2.0v typ 1.5vo 27pf ( 30pf ) 0.45uh pf 0 0 0 0 0 0 16 ? 25ch. 18.73 ?15.86pf 27pf 0.45uh - 0 0 0 0 0 1 16 ? 25ch. 18.73 ? 15.86pf 30pf 0.45uh 0.6 0 1 0 0 0 1 01 ? 04ch. 18.73 ?15.86pf 27pf 0.45uh 1.6 0 0 0 0 1 0 05 ? 10ch. 18.73 ? 15.86pf 27pf 0.45uh 1.2 0 0 0 0 0 1 11 ? 15ch 18.73 ? 15.86pf 27pf 0.45uh 0.6 0 1 1 1 0 0 01 ? 06ch. 18.73 ? 15.86pf 30pf 0.45uh 7.0 0 1 1 0 1 0 07 ? 15ch. 18.73 ? 15.86pf 30pf 0.45uh 5.8 12 bits reference program divider. pd_tx ld pdt fref (a) (b) (c) fr1 fr2 14 bits tx. program divider. 2loi tif ref.freq ? 4 ? 25 fref ? 4 fref ? 25 tif ? n
s1t8527c 1 chip clp subsystem ic 18 figure 2. ( phase detector / lock detector output waveform ) ref.freq. pdt ld tif ? n
1 chip clp subsystem ic s1t8527c 19 application circuit (base set) 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 2mi 1mo 1loi 1loi vco rx 1mi 1mi gnd (pll) pdr v ref(pll) v cc(pll) tif v ref (comp) alc epi erc eo sai sao1 sao2 v cc(comp) gnd (comp) cpi+ cpi- 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 pdt co sfi sfo cdo/ldt gnd (pll) clk data en lbd agic crc 2ldi 2loi 2mo vcc (rx) li ld gnd (rx) qci rao dsci dsco cdo rx ant tx tx vco ant l1 1.8uh fet1 25k544 duplex c51 10n r37 100 fet2 10.7mhz r35 22 c48 10n c46 10n t4 (aw) c47 30p c49 100n r36 56k t3 (ay) c50 r39 t2 (ay) c52 0.47uf 3.9k r40 10k c57 47n 10 r41 c56 10n c58 10n c53 10uf r10 10k r11 10k r44 10k c17 12n c24 2.2uf c26 1.0uf to micom (mcu) data from micom (mcu) to micom (mcu) r19 68k r14 560 c28 100n c29 10n r22 10 c30 1.0n r24 33k r25 51k c32 100n c33 3.3uf c34 100n r26 120k c35 4.7uf r2 50k c37 10n c38 220uf l5 22uh c39 10n r28 10k r29 10k vr1 50k r30 27k r31 27k c40 10n r33 22k r32 470k c41 33n r34 51k t5 c42 68n c43 10n flt3 455khz c44 33p y1 10.24mhz c45 20p cvi 20p s1t8527c c25 3.3uf compressor input main power rx out rx data out 2p
s1t8527c 1 chip clp subsystem ic 20 application circuit (hand set) 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 2mi 1mo 1loi 1loi vco rx 1mi 1mi gnd (pll) pdr v ref(pll) v cc(pll) tif v ref (comp) alc epi erc eo sai sao1 sao2 v cc(comp) gnd (comp) cpi+ cpi- 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 pdt co sfi sfo cdo/ldt gnd (pll) clk data en lbd agic crc 2ldi 2loi 2mo vcc (rx) li ld gnd (rx) qci rao dsci dsco cdo rx ant tx tx vco ant l1 1.8uh fet1 25k544 duplex c51 10n r37 100 fet2 10.7mhz r35 22 c48 10n c46 10n t4 (aw) c47 47p c49 100n r36 120k t3 (ay) c50 r39 t2 (ay) c52 1.0uf 4.3k r40 1.0k c57 47n 10 r41 c56 10n c58 10n c53 10uf r10 22k r11 10k r44 10k c17 12n c24 2.2uf c26 1n to micom (mcu) data from micom (mcu) to micom (mcu) r19 20k c28 100n c29 10n r22 10 c30 1.0n r24 33k r25 51k c32 100n c33 3.3uf c34 100n r26 120k c35 4.7uf r2 50k c37 10n c38 220uf l5 22uh c39 10n r28 10k r29 10k vr1 50k r30 27k r31 27k c40 10n r33 22k r32 470k c41 33n r34 51k t5 c42 68n c43 10n flt3 455khz c44 33p y1 10.24mhz c45 20p cvi 20p s1t8527c c21 6p 2p c25 3.3uf compressor input main power rx data out 1 2 c31 10p spk c36 68n

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